Magillem provides to customers in the electronic industry tools and services that drastically reduce the global cost of complex design.

Magillem has developed an easy to use, state of the art platform solution to cover electronic systems design flow challenges in a context where complexity, interoperability and design re-use are becoming critical issues to manage design cycle time of SOC. Main benefits include:

• Maximizing Design and IP Re-use
• Using a virtual platform to configure their system and IPs
• Controlling the Design Flow
• Exploring their Design Flow architecture and optimizing it
• Improving their independence from CAD tools vendors
• Improving interoperability, communication
• Benefiting from better user interfaces to raise productivity
• Relying on worldwide adopted standards

Our Motto:

Methodology tools should adapt to the trends in SoC design and help streamline the design flows without disrupting existing processes

IP Description

The goal of this first step is to package all the components of an IP library into XML files in accordance with the IP-XACT schema (standarized as IEEE1685), which describes the syntax and semantic rules for the description of three kinds of elements: the bus definitions, the components and the designs (in which components are instantiated). Thus the purpose of the IP packaging is to fill in for each component the XML fields that describe its attributes: physical ports, interfaces, parameters, generics, register map, physical attributes, etc. An important part of the schema is dedicated to referencing the files related to the different views of a component: a view may be for instance a simulable model in a specific language (VHDL, Verilog, SystemC, etc) or documentation files (e.g. PDF, HTML, Framemaker). This work facilitates future reuse of existing components, because all of their features are easily accessible for its integration and configuration in a bigger system, as it will be explained in the next step.

System Description

After this step, is it possible to import, configure and integrate components into the system, assemble the design, resolve connections issues, and automate design tasks, thus lightening the verification steps. Some examples of the use of IEEE1685™ standard at this level are: partial or full automation of design assembly and configuration, detection of communication protocols mismatch, toplevel netlisting, or automatic customization of compilation and simulation of designs. The work that is the topic of this paper takes place in this category: managing the generation of specific verification code from the IEEE1685™ description of a system and its components.

Design Automation and Flow control

The third step of the methodology, depicted in the previous figure, aims at linking the design activities around the centric IP-XACT (IEEE1685™) database by means of a dedicated environment which provides access to the IP-XACT (IEEE1685™) information. The tool suite chosen for this study (Magillem environment) provides an IP Packager, a Platform Assembly tool, as well as a Generator Studio to develop and debug additional TGI-based generators. These may be encapsulated within the IP-XACT (IEEE 1685™) representation of an IP and may for example simply launch the execution of a script, getting arguments values from the design description in IP-XACT (IEEE1685™), or be on the contrary a more complex engine, the role of which would be to modify the design itself (e.g. add connections, insert adapters, or configure components).

Principle schema for an IP-XACT (IEEE1685™) standard flow

Checkers can also be developed and used to verify design rules at some point, before going further in the design flow. Besides, IEEE1685™ standard provides mechanisms to describe the sequences of chained generators and checkers.

Advanced design flow architecture

This last step in the methodology has a high potential because it exploits all features described previously and allows the actual implementation of advanced ESL activities, such as architecture exploration or software application automated mapping on a hardware platform. These examples show the complexity that has to be managed by the three first steps: all components must be packaged and their configurability must be taken into account; the design assembly automation should be maximized, while any architecture choice should be handled. At last, the generator chains, as defined previously, can be configured and controlled by supervisor engines: for instance a validation sequence will configure and execute several times the generators dedicated to testbench configuration, compilation and simulation.

WE ARE HIRING

Magillem was present at DAC on Cadence EDA theater.

March 2011: