Magillem Design Services is participating in the following R&D collaborative projects: 

BEYOND DREAMS

Partners: STMicroelectronics, Infineon Technologies Austria AG, Infineon Technologies AG, NXP Semiconductors, Robert Bosch GmbH, Dizain-Sync, Twente Institute for Wireless and Mobile Communications, CEA-LETI, Fraunhofer IIS/EAS, Vienna University of Technology, TIMA/Institut Polytechnique de Grenoble, Université Pierre et Marie Curie, Delft University of Technology (TU Delft)

Design Refinement of Embedded Analogue and Mixed-Signal Systems (DREAMS) is a joined effort of the European semiconductor companies, together with leading European Universities and research institutes, to address the design issues for these mixed-signal systems. The overall objective of the Beyond DREAMS project is to improve the competitiveness of European industries in the domain of embedded mixed-signal system design by reducing the entire design time and cost of heterogeneous SoC and SiP. To achieve this overall objective, Beyond DREAMS will improve the design refinement process of EAMS by providing a methodology, a simulation and modelling framework, standardized languages, libraries and modelling formats that guide and instruct designers to perform architectural refinement of analogue/mixed-signal/RF sub-system design in the context of digital HW/SW co-design. It offers a modelling and simulation platform to validate communication and network protocols, architectures, analogue/RF subsystem specification or properties of the physical implementation in the early design space exploration phases. Objective is to develop modelling techniques which will be standardized, where the proof-ofconcept implementation will become freely available as open-source software. In addition to this, a design environment facilitating IP integration, modelling and simulation is required. A unified design framework and flow, which should be based on standardized meta-data model descriptions, should bring the different design disciplines together, enabling design/IP reuse and interfacing with third-party design and simulation tools.

Start of the project: June 2008, Duration: 3 years 

SOCKET

Partners: ASTRIUM, AIRBUS, CEA-LETI, CNES, Université Paul Sabatier (IRIT), UBS - LESTER, PSI-S, STMicroelectronics, Thalès R&T, INPG/TIMA

The evolution of the technology and the application needs leads to design more and more complex embedded systems both at hardware level and software level. Mastering this complexity, in order to improve the time cycle and the costs of the design and the validation/certification of the critical embedded systems, is a key point to ensure the success of future industrial projects. Indeed, the mastering of a “seamless” design flow built upon a set of integrated engineering tools, allowing to validate/qualify/certify any critical embedded systems based on SoC (System On Chip) is needed for aeronautic, space, energy, automotive and health applications.

Thus, the goals of the project are: 

• Combine the partners effort to propose some methodological and process solutions for the full design flow of critical embedded systems, by using the cross-competencies of the industrial and academic partners, 
• Define a “seamless” development flow, integrating the equipment qualification/certification, from the system level to the Integrated Circuits (IC) and associated SW,
• Master the “system dimension” (SW + HW) into the SoC integration issues,
• Master the complexity, the time cycle reduction, the design optimization of SoC-based systems,
• Evaluate the HW simulation models (from the design flow) usage for the integration and the validation of the critical embedded SW,
• Propose a prototype of an Integrated Development Environment based on open standards of the market, implementing the SoCKET process and adaptable with other tools and for other application domains

SOCLIB

SOCLIB goals aims at building an open platform for modeling and simulation of multi-processors system on chip, that can be used by both universities and industrial companies. The core of the platform is a library of simulation models for virtual components (IP cores), with a guaranteed path to silicon. The goal is to create the largest possible cooperation project at European level, in order to share the development costs.  This project begun in February 2007 and will end in January 2010. Website

Start of the project: February 2007, Duration: 3 years