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Description
Entering the market with a product targeting the traditional need of IC designers to manage the Registers, MAGILLEM is offering a brand new approach: Customers do not have to choose between an Excel based Register capture system, disconnected from their design, or an expensive, dedicated Register management tool, still not addressing the issues of collaborative work. Cost effective, and non-compromising, MRV by Magillem offers a Register View of IP-XACT Systems and IPs:
Features
- Complete Register and Bitfield editor
- Instead of a simple viewer
- Move and resize Bitfields
- Interactive update of the bitfields at the tip of the mouse
- Memory Map editor
- Move and replace memory blocks
- Drag and drop inside the memory map
- Copy/Paste
- Of memory blocks in memory map
- Visual identification of overlaps
- True synchronization with RTL or ESL platform
- Visualize and edit the full project hierarchy
- True Hierarchical description
- Single source based solutions can´t work for the next generation! Concurrent developments handle more than 500 different xml files containing memory map fragments. The relationship and the ordering, hierarchy defined in the project must be preserved.
Architecture
| Advanced Parameterization, Reuse and Collaborative strengths to describe Modal Hierarchical Components, Registers and Memory-Maps |
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Zero learning curve GUI with graphical editors allowing for the fast capture of registers and memory maps, IP-XACT (robust but tedious) is hidden behind comfortable designer–oriented capture graphical interface |
| Flexible Generators Customization performed thru native Object Oriented API, template-based Engine or IP-XACT TGI |
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Leading-edge Textual Input Language compliant with state-of-the-art Magillem, Eclipse and IP-XACT Technologies |
Description
OS:
Windows, Linux
MRV Basic:
Includes Generators templates
MRV Premium:
Generator customization GUI, RDL, Full synchronization with ESL /RTL platform
Related Products
MPA and MGS
MRV is used in Magillem ESL, RTL, Board, FPGA AMS and Verification solutions.
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User Case
One of the biggest challenges for any decent register centric solutions is to ensure the HW/SW synchronization. Synchronization means that different set of data evolve concurrently, representing different register facets or views of the IP targeting a specific use model: firmware data, hardware data, verification, documentation...
For this first-tier customer, one of the top ten SOC designers worldwide, the problem is acute : views need to be merged or updated at some milestones in the flow. These views are owned by different groups of people having the rights and the knowledge for any modification of the dedicated facet. The Register centric design- environment must have the features to handle such synchronization, version handling, data inference... So far, all data were mixed up within the same bucket, jeopardizing data filled in by other owners. Same bucket doesn´t mean a unique file. Synchronization doesn´t mean that all data generated in different targeted languages come from the same unique source. They come from multiple sources, multiple files which are now synchronized with MRV, ensuring that they comply with the same IP definition model and complement each others.
"The request for hierarchical views of the registers is also fulfilled thanks to MRV, the quality of its graphical interface improves the productivity drastically, for the first times my register specification is synchronized with my RTL and ESL design even during my bottom up implementation! The comfort of interactive immediate handling of register bit fields and blocks of memory maps via the MRV GUI make this new generation register management tool an undeniably compelling offering for the designers" says Jim C, Senior Hardware Project Lead."
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