We deliver a set of IP, available at RTL or TLM. The goal of these IPs is to solve heterogenity issues in systems (communications, protocols, level of abstraction). All the IPs are silicon proven with multiple designs on ASIC or FPGA(Xilinx, Altera,..).

• RTL and TLM bus models 
  • AMBA AHB
  • AMBA APB
  • OCP
  • VCI

• Wrappers & Bridges
  
  • Master & Slave AMBA AHB / VCI bus wrappers
  • Master & Slave AMBA AHB / OCP bus wrappers
  • Design Kit OCP / AMBA, AMBA AHB / OCP bus wrappers, AMBA APB / OCP bridge and wrappers

• Memory Controllers
  • Multi Channel DDR SDRAM Memory Controller
  • Multi Channel SDR SDRAM Memory Controller

• Bus Functional Models (BFMs)
  
  • Traffic generator

• Transactors & Adaptors 
  • Magillem donates to the OCP consortium the protocol adaptors TL2/TL1/TL0

• OCP based IP Creator (protocol wrappers)
  • Convert a fifo based or a memory based communication interface into a OCP socket