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SystemC Training

The objective of this course is to understand SystemC semantics, control simulations, learn how to refine a system through different levels of abstraction and use transactional communication with channels and their APIs. This course presents a description of the SystemC language for high-level modelling: how it fits in the system-level design flow, what are the differences with HDL languages. This course describes the fundamentals of SystemC language, and the functioning of SystemC scheduler. In the last part, it shows how to use transactional communication in a system.

The three days course contains the following agenda: 

  • SystemC overview: general presentation, system modelling, language fundamentals, abstraction level concepts.
    lab: create a system with different modules, connect them and launch the simulation 
  • High level SystemC: presentation of the key structures of the communication (interface, port, channel), communication refinement.
    lab: describe a system based on OSCI’s simple_bus example to connect masters to slave, use OCP-IP’s transactional channel and API to execute OCP communication
 
The level of software or hardware designers attendees must be intermediate and knowledge is required on C/C++ with notions of VHDL or Verilog. The course is 1/4 lecture, 3/4 labs. The course can be extended to 5-days with in addition:
  • C++ fundamentals for SystemC, 
  • basic RTL SystemC, 
  •  more transactional labs