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Building a Portable Stimulus flow based on Magillem IP-XACT Packaging
The upcoming Portable Stimulus standard from Accellera provides an abstract format for declaratively specifying verification intent for a given design-under-test (DUT), enabling multiple implementations of that intent to be gen-erated for the different verification platforms (simulation, emulation, prototypes, etc.) used throughout a typical verification flow. Using IP-XACT (IEEE Std 1685-2009) to characterize the IP blocks of our System-on-Chip (SoC) designs captures the designers’ knowledge of a given block using machine-readable meta-data that can be used by an SoC assembly tool to build the actual design. Each of these standards can increase productivity by enabling reuse from the IP block to SoC level. This paper examines ways to achieve even better results by combining them in our verification flow.
Straightforward IP Integration with Ip-XACT RTL-TLM switching
This paper gives the results of experimentations done for the packaging of a USB OTG controller respecting the IP-XACT schema provided by the SPIRIT consortium. It presents the advantages and the technical facts for an IP provider to deliver standardized files package, bringing great advantages for documentation, integration and verification purposes. In particular, it is shown how to handle interfaces, registers and multi abstraction level descriptions of the component. This paper also presents the exploitation of the IP-XACT files for the IP testbench and the simulation.
HW/SW interface generation flow based on abstract models of system applications and hardware architectures
The growing complexity of hardware architectures to meet the increasing performance requirements of the system applications reveals new programming problems, in particular when we aim to use a same hardware platform for different applications. In this paper, we present a code generation flow to deploy system applications over hardware architectures based on abstract descriptions. Our approach is defined in two steps: a front-end step which deals with abstract description of the application, the architecture (in extended IP-XACT), the mapping, and a back-end step which incorporates specific platform details necessary for HW/SW interface generation.
Using IEEE 1685 standard (IP-XACT) for specifications and requirements traceability in critical system design flow
The raising complexity of systems tends to increase the difficulty for large integrator company to manage the exchange of specifications between design and verification teams involved in the process cycle. This problem is even more important in critical system area where requirements traceability is mandatory to fulfill obligations of qualification and certification processes. In order to develop the mechanisms that provides the capability to manage in an efficient and automated way the requirements traceability, we show in this paper that tooling upon the IP-XACT IEEE 1685 standard can bring an important part of the solution.
Design environment for the support of configurable Network Interfaces in NoC-based platforms
IP-based platforms with Network on Chip (NoC) are one solution to support complex telecommunication applications. In this context, NoC architectures targeting high throughput applications tend to have configurable Network Interfaces (NI) and routers for reuse and performance purposes and aims at providing advanced communication and computation services. Unfortunately, these Network Interfaces are increasingly complex to parameterize and to program, while the deployment tools taking into account the low level architectural details are still non existent. This work focuses on providing methods and tools to easily and efficiently deploy applications on IP and NoC based platform with configurable NI. Configurable NI offer primitives to synchronize and schedule the communication and the behaviour of IPs. Our code generation flow takes as input an abstract model of the HW platform, of the application and of the mapping, and generates most of the required configurations.
A Design flow for critical embedded systems
The SoCKET project (SOC toolKIT for critical Embedded sysTems) gathers industrial and academic partners to address the issue of design methodologies for critical embbeded systems. They work towards the definition of a “seamless” design flow which integrates qualification and certification, from the system level to integrated circuits and to software. This paper sketches such a design flow and the associated methodologies, and brieffly drescribes its application to industrial case studies.
A configurable test infrastructure using a Mixed-Language and Mixed-Level IP integration IP-XACT flow
We present a reusable text infrastructure of RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT standard. The test infrastructure is configurable, meaning that specific configurations can be generated from a template. The main part of the components in the test infrastructure is implemented using the SystemC TLM2 standard. A small part is implemented in VHDL. The design technology to generate configurations uses the IP-XACT standard. We present an application of the resuable test infrastructure for randomized IC verification. Our result demonstrate an efficient integration flow for mixed-language and mixed-level IPs through flow automation.
AMS System-Level verification and validation using UVM in SystemC and SystemC-AMS
The automotive trends is to increase the electronics systems inside vehicles. The complexity of such systems is rising with the number of components involved on the one hand and on the other hand on the tighter interaction between these components, being analog, digital hardware or software. The verification of Electronic Control Systems (ECU) becomes more and more challenging. In this paper we show that the Universal Verification Methodology (UVM), initially developed for digital systems, which consists in clearly distinguishing between the test scenario, described in an abstract way, the Device Under Test (DUT) and the test environment that translates the test to the DUT interface, can be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS library implemented above SystemC and its AMS extension SystemC-AMS. This approach is used to verify two ECUs from automotive industry. The first use case shows how UVM can be used for the simulation-based verification of a complex mixed-signal design. The second use case shows how UVM can be used on a Hardware In the Loop (HIL) system to verify and validate a FPGA prototype.
Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT
This paper will present a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC-AMS and IP-XACT. The UVM foundation elements such as test, environment, UVC (Universal Verification Component), transactions and associated configuration objects are introduced, which are packaged by means of IP-XACT vendor extensions. The benefit is to facilitate the (re)use of UVM components and environments by providing a readable and configurable test platform description, to trace the requirements of tests, and to generate automatically the entire UVM environment and simulation build flow after configuration of the test scenario. The automation technology is based on IP-XACT and uses new capabilities of the Magillem tools solutions.
Rigourous Framework for hardware-software co-design of embedded systems
This paper presents how the project ACOSE provides solutions to solve the following issues:
  • Managing application requirements which are transvers: functionality, performances, consumption, security, etc…
  • Hardware / software partitioning
  • Safety constraints requiring rigorous design
  • Choice and configuration of the target hardware platform
  • Design and deployment issues within industrial contexts
  • Application code generation for the target platform
  • Simulation, co-simulation, virtual prototyping
  • Requirement traceability and specifications impact analysis
  • Performance analysis
  • A power consumption estimation approach for embedded software design using trace analysis
    With the explosion of advanced power control knobs such as dynamic voltage frequency scaling, mastering energy constraints in embedded systems is becoming challenging for software developers. Several power estimation techniques have been proposed over the past years, from electrical level to more abstract models such as SystemC/TLM. They offer various tradeoffs between performance and accuracy, but suffer from a number of shortcomings. They are expensive and time-consuming, requiring intricate models of the architecture and finally, fail to be applied from the software developer perspective. In this paper, we propose a lightweight and cost-effective approach suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without loosing accurancy.
    Integrated Architecture exploration workflow: a NoC-based case study
    Compute-intensive applications can greatly benefit from the flexibility of NoC-based heretogeneous multi-core platforms. However, mapping applications on such MPSoC is becoming increasingly complex and requires integrated design flows. We conducted a case study to evaluate the benefits of an integrated design flow for the mapping space exploration of a real telecommunication application on a NoC-Based heterogeneous platform. Thanks to the flow, we simulated several virtual platforms and several mappings of our application on each. This approach drastically lowers the required skills and the time needed for design space exploration.
    A SystemC Extension of Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes
    The design possibilities offered by IoT devices in an ever-expanding market require ever-shorter virtual prototyping iteration cycles. In this context, generating at least the SystemC platform’s structure, from an IP-XACT description, is a key factor for improving the iteration turnaround time. However, critical constraints such as field access type or bit width, and more generally the documentation of platform elements, are conventionally absent from the development environment.
    Using Virtual Prototypes to improve the Traceability of Critical Embedded Systems
    This paper explains how the combination of innovative traceability techniques with advanced Virtual Prototyping execution environment helps detecting and locating critical embedded system bugs located at the frontier of Hardware and Software, by tracing the dependencies between all the objects of any kind such as requirements, specification, documentation, hardware or software meta-data.