Training

Accelerate your Magillem product skills with our classroom trainings.

We offer five standard types of training programs on Magillem tools, and a unique training on IP-XACT and IP-XACT methodology.

We can also build a custom training program for your teams.

BASIC Training


Day 1:
9am-1pm: IP-XACT overview

– History and key concepts
– How to read and navigate in the IP-XACT specification/schema
– Main IP-XACT constructs

2pm-6pm: IP-XACT in depth

– Protocol descriptions (Bus Definition & Abstraction Definition)
– The Component schema
– Design and Design Configuration
– Last but not least the API (TGI)

Day 2:
9pm- 1pm: IP-XACT for a purpose

– IP-XACT for connectivity
– IP-XACT for registers
– IP-XACT for file management

2pm-5pm: Use cases

– Leveraging IP-XACT for advanced flows
– Leveraging IP-XACT for Verification

5pm-6pm: Knowledge management and Q&A

PREMIUM Training


■ Duration: Three weeks
■ Location: On site or at Magillem´s premises
■ Resources: One Magillem Expert engineer
■ Premium Training seminars are usually planned for groups of 4 people max
■ Agenda: Flow analysis and requirements
■ Content:
IP repository examples study

– Packaging of one fix IP
– Packaging of one multiple parameter IP
– Packaging of one configurable IP

Study of customer flow and requirements

– For the automation of the interconnections, netlist generation Verilog, VHDL, …
– Concurrent development and multiple views support with IP-XACT. How to assemble, verify and merge the IP-XACT fragments
– Flow analysis
– Packaging / Flow
– Flow for RTL platform assembly: mix RTL mode
– Flow for verification (simulators, BFMs, …)

﹥ Nc, Modelsim, Vera, VCS, Specman

– Flow for synthesis

﹥ SDC files, timing extraction

– Flow for Design For Test (DFT functions need to be identified by the packager)

﹥ With the objective of automating milestones of tests insertion

– Flow pour I/O MUX-ing (merge, insertion of component)
– Directory structure modification, where to store the IP-XACT files METADATA folders
– Global definition for the “bus definition” or local definition

﹥ Update the connections
﹥ Update the parameters

REGISTER Training program


Day 1:
9am-1pm: IP-XACT elements for registers

– Memory Maps
– Registers blocks and dimensional
– Registers and dimensional
– Bitfields
– Enumerations
– Alternate registers

2pm-6pm: Special registers representation

– Templated registers
– Templated bitfields
– Wide bitfields
– Other registers (indirect, shadow…)

Day 2:
9pm- 1pm: Register configurability and system

– Configurable register elements
– Model parameters
– Choices
– Setting / resolving register configurable elements

2pm-5pm: Register flow

– Slave Bus Interface and Memory Map
– Design and system map
– Tight Generator Interface
– Generator chains

5pm-6pm: Knowledge management and Q&A

CONNECTIVITY Training program


Day 1:
9am-1pm: IP-XACT elements for connectivity

– Abstraction Definition
– Bus Definition
– Bus Interface
– Ports
– Configuration
– Design

2pm-6pm: Simple connectivity

– Protocol based (interconnect)
– Wire based (AdHoc)
– Hierarchy

Day 2:
9pm- 1pm: Advanced connectivity

– Representation of special connectivity elements
– Feed through
– Phantom ports
– Glue Logic

2pm-5pm: Connectivity flow

– Power insertion
– DFT
– IO

5pm-6pm: Knowledge management and Q&A

VIRTUAL PROTOTYPING Training


Day 1: Automatically create and validate a SystemC IP from its specification
■ Introduction to Virtual Prototyping
■ Quick SystemC refresh
■ Quick tour of IP-XACT
■ Package and validate a Virtual IP
Step-by-Step flow

– setup
– update IP-XACT file and generate SystemC code
– update SystemC code (add behavior)
– validate with SW testbench

■ Debug and configure (with gdb) both the systemC and the eSW
■ Hands-on (lab1)
■ Build and validate a simple SystemC ADC IP
Day 2: Automatically create and execute a reusable and reconfigurable Virtual Prototype
■ Assemble, configure and execute a complete Virtual System

Step-by-Step flow

– setup
– plug and connect generic IP-XACT components
– swap components
– manage hierarchy
– generate SystemC code
– build and compilation flow

Configure the Virtual Prototype

– run-time vs compilation-time parameters
– dependent parameters

■ Execute, Debug and Analyse results
■ Hands-on (lab2)
■ Build a basic Virtual Prototype capable of booting Linux and running an embedded application SW
■ Wrap-up
Day 3: For advanced-users, SystemC modeling